The present invention relates generally to a digital circuit for, and a method of, synthesizing an input signal. The invention also relates to a computer program product for carrying out the method.
Two main embedded circuit topologies are typically used for low jitter frequency synthesizers, namely, phase-locked loops (PLLs) and delay-locked loops (DLLs). A PLL typically uses a voltage controlled oscillator (VCO) to generate an output clock signal which is frequency and phase locked with an input clock signal. Typically, signal locking is achieved by adjusting an input voltage of the VCO. A characteristic of the PLL is that the phase error (noise) generated internally in the VCO is circulated when each new cycle is started at the end of a previous cycle as a result of the feedback arrangement. The phase error accumulation is however limited in that the control loop continually checks the mismatch of the input and output clock phases. If the control loop is fast to respond to the phase error, the error accumulation will, accordingly, be reduced. However, if the control loop is slow to respond to the phase error, the phase error accumulation can grow significantly before it is restrained. The latter situation may pose a problem for PLLs with low frequency input clocks as the control loop in these circumstances is required to be very slow. As a result of the sluggishness of the control loop, the VCO phase error may be allowed to accumulate and, for some systems, the phase error accumulation is a key parameter and thus, due to this limitation, a PLL will not suffice. Typically, in these circumstances, a DLL provides an alternative typology in that is addresses the phase error accumulation problem. In these circumstances, the reference signal is typically an input to a voltage control delay line (VCDL) which, when in lock, will delay an output signal by one period relative to the input signal. Thus, an output clock edge or the output signal may then be compared to a clock edge of an incoming signal and the VCDL is then adjusted until the edges are aligned. As each cycle is started by the incoming clock edge, the phase error accumulation or drift is reset to zero at the beginning of each cycle. An example of a draw back of conventional DLL structures is seen when it is used to scale the incoming signal by a large multiple. For example, to scale up the frequency of an incoming signal by a factor of 10, typically 10 delay units in series are necessary which, when in lock, together equal the period of the incoming clock. Outputs from these 10 units are then typically used to create delayed phases of the incoming clock and, using combinational logic, the phases may be used to generate a 10 times clock. It will appreciated however that in order to achieve a large multiplication, for example, of two thousand, the required delay elements connected in series would occupy a substantial area of an embedded circuit. Further, as the number of delay elements increases, the depth of logic to combine the phases to produce the output clock becomes more complicated.
According to the invention, there is provided a digital circuit for synthesizing an input signal to produce an output signal, the circuit including:
a delay unit with a delay input and a delay output;
a switch to selectively route the input signal to the delay input whereafter the switch routes the delay output to the delay input; and
a controller to control the delay unit in response to the input signal and the output signal.
Further in accordance with the invention, there is provided a method of synthesizing an input signal, the method including:
switching a delay input of a delay unit in response to the input signal; and
switching the delay input in response to an output signal of the delay unit for a predetermined number of times whereafter the delay input is switched again in response to the input signal.
The invention extends to an embedded circuit which includes a delay-locked loop for synthesizing an output signal from an input signal, the delay-locked loop including:
delay circuitry with a delay input and a delay output;
switching circuitry connected to the delay circuitry, the switching circuitry for selectively triggering the delay input in response to the input signal whereafter the switching circuitry triggers the delay input in response to the output signal; and
control circuitry to control operation of the delay circuitry.
The invention also extends to a computer program product stored in a medium readable by a computer, the medium including instructions which, when read by the computer, cause the computer to:
switch a delay input of a delay unit in response to an input signal, the delay unit providing an output signal which is delayed relative to the input signal; and
switch the delay input in response to an output signal of the delay unit for a predetermined number of times whereafter the delay input is switched again in response to the input signal.
The invention extends further to a machine-readable medium storing a description of a circuit, said circuit including:
a delay unit with a delay input and a delay output;
a switch to selectively route the input signal to the delay input whereafter the switch routes the delay output to the delay input; and
a controller to control the delay unit in response to the input signal and the output signal.
Other features of the present invention will be apparent from the accompanying drawings and from the detailed description that follows.